About Syed Mannan Saood
I'm a systems developer and software engineer with a deep passion for building high-performance, kernel-level, and low-level software from scratch. My areas of focus include Rust, eBPF network observability, peer-to-peer protocols, and silicon hardware verification.
Over the past few years, I have engineered custom Kubernetes observability pipelines, designed virtual file system layers for Android sandbox environments, and authored NAT hole-punching P2P shells in Rust. My background bridges the gap between hardware-level logic gates (such as SystemVerilog DMA controllers and NoC QoS routers) and scalable cloud platform engineering.
Project Repositories & Interactive Workbenches
Software Systems
Sennet — Kubernetes Observability System
Role: eBPF Kernel Probing & Telemetry Compiler
Description: SaaS-ready Kubernetes observability platform. Utilizes kernel-space eBPF probes to capture deep socket descriptors and inspect payloads in real-time, enabling cost estimates and network maps without container sidecar overlays.
Keywords: Rust, eBPF, Go, Kubernetes, Observability, Telemetry
termi — Android Terminal Emulator & VFS Bridge
Role: Virtual File System Architect & Rust Daemon Developer
Description: Next-generation Android terminal emulator designed in Rust. It utilizes a custom SAF-VFS storage bridge translating standard POSIX file operations into Google Document SAF requests, bypassing Android sandbox permissions.
Keywords: Rust, Android, VFS, Google Storage, Sandboxing
Punch — CLI Peer-to-Peer NAT Tunnel
Role: P2P NAT Protocol Architect
Description: CLI networking tool for secure peer-to-peer remote shells and file transfers. Implements NAT traversal / UDP hole-punching using STUN protocols, establishing direct tunnels without third-party middle servers or VPN layers.
Keywords: Rust, P2P, QUIC, Iroh, NAT Holepunch, Security
Dhani — High-Speed Trading Middleware
Role: High-Performance API Architect
Description: High-speed trading middleware bridging legacy MetaTrader 5 (MT5) with modern fintech APIs (Dhan). Implements real-time Symbol translation, position synchronization, and concurrent latency audits.
Keywords: Go, Fintech API, MT5 Integration, Latency auditing, Concurrency
Silicon & RTL Engineering
QoS Network-on-Chip (NoC) Router
Role: IP Core RTL Design & Verification
Description: Advanced 3x3 Network-on-Chip packet router IP core. Designed with virtual channel flow control, providing independent routing queues (VC0/VC1) to isolate high-priority traffic and prevent downstream system bottlenecks.
Keywords: SystemVerilog, RTL, VLSI, UVM, Hardware IP Core
2-Channel DMA Memory Controller
Role: RTL Designer & Verification Engineer
Description: High-throughput 2-channel direct memory access controller IP block. Implements Round-Robin read/write arbitration cycles to maximize memory bus throughput without CPU intervention.
Keywords: SystemVerilog, Verilog, RTL, UVM, DMA, Hardware